Novel clamp circuits for IC power supply protection

Abstract

Biased and terminated p-n-p transistor chains are made from floating n-wells in p-substrate CMOS and used for power supply ESD clamps. The p-n-p gain may allow a compact termination circuit to be used, resulting in a stand-alone clamp. Bipolar p-n-p action accounts for unwanted low-voltage conduction as well as for very desirable clamping of power supply overvoltages. Bias networks are used to prevent excessive leakage at high temperature. These devices are becoming crucial to success in ESD product testing of CMOS integrated circuits.