E. Worley

Sub-micron chip ESD protection schemes which avoid avalanching junctions

E. Worley, Ratnesh Gupta, B.E. Jones et al. · 1995 · 109 citations

Hardware Security, Electrical Engineering, Engineering +10

Distributed gate ESD network architecture for inter-power domain signals

E. Worley · 2004 · 41 citations

Low-power Electronics, Electrical Engineering, Engineering +14

The gate bias and geometry dependence of random telegraph signal amplitudes [MOSFET]

S. T. Martin, G.P. Li, E. Worley et al. · IEEE Electron Device Letters · 1997 · 36 citations

Device Modeling, Electrical Engineering, Semiconductor Device +15

Theory of the fully depleted SOS/MOS transistor

E. Worley · Solid-State Electronics · 1980 · 31 citations

Engineering, Physics, Nanoelectronics +4

A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies

Steven H. Voldman, Warren Anderson, R.A. Ashton et al. · 2003 · 25 citations

Electrical Engineering, Esd Metrics, Engineering +13