IEEE Transactions on Electron Devices · 1993 · 603 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsVlsi DesignCmos Circuit DesignDelay ModelingIntegrated Circuit DesignInterconnect TechnologyTiming AnalysisVery-large-scale Integration LayoutInterconnect DelayInterconnect Delay AnalysisInterconnect Delay ModelingInterconnect Delay OptimizationInterconnect ModelingInterconnect OptimizationVlsi ImplementationVoltage-dependent Delay
A closed-form formula for a waveform of the RC interconnection line with practical boundary conditions is derived. Expressions are also derived for the voltage slope and transition time of the RC interconnection and for coupling capacitance and crosstalk voltage height, which can be used in VLSI designs. Using the expressions, the optimum linewidth that minimizes RC delay and the trend of RC delay in the scaled-down VLSIs are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Approximation of wiring delay in MOSFET LSI
T. Sakurai · IEEE Journal of Solid-State Circuits · 1983 · 409 citations
Signal Delay in RC Tree Networks
P. Penfield, J. Rubinstein · 18th Design Automation Conference · 1981 · 142 citations