Interconnect Optimization

Interconnect Optimization is a physical design methodology within Very-Large-Scale Integration that focuses on minimizing signal delay, power consumption, and area占用 by strategically refining the routing, placement, and electrical characteristics of on-chip interconnects.

730

Publications

33.7K

Citations

Authors

420

Institutions

Publications per year

2017–2026

Parents

Data Movement OptimizationPhysical DesignVery-large-scale Integration Layout

Publications

730

Force-directed scheduling for the behavioral synthesis of ASICs

Pierre Paulin, J.P. Knight · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1989 · 1.1K citations

Engineering, Computer Engineering, Computer Science +16

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Kaustav Banerjee, S.J. Souri, Pawan Kapur et al. · Proceedings of the IEEE · 2001 · 1K citations

Engineering, Computer Engineering, Electrical Engineering +17

Development of interconnect materials for solid oxide fuel cells

Wenbo Zhu, S.C. Deevi · Materials Science and Engineering A · 2003 · 779 citations

Engineering, Materials Engineering, Materials Science +14

GARNET: A detailed on-chip network model inside a full-system simulator

Niket Agarwal, Tushar Krishna, Li-Shiuan Peh et al. · 2009 · 759 citations · Full text

Engineering, Computer Engineering, Computer Science +17

Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs

T. Sakurai · IEEE Transactions on Electron Devices · 1993 · 603 citations

Engineering, Computer Engineering, Electrical Engineering +17

1–5 of 730

Authors

JC
Jason Cong
University of California, Los Angeles, United States
20 publications · 1.1K citations
18
h-index
JM
J.D. Meindl
Georgia Institute of Technology, United States
21 publications · 1.3K citations
17
h-index
AB
Andrew B. Kahng
University of California San Diego, United States
14 publications · 471 citations
13
h-index
AN
Azad Naeemi
Georgia Institute of Technology, United States
15 publications · 358 citations
12
h-index
LH
Lei He
University of California, Los Angeles, United States
13 publications · 936 citations
12
h-index

1–5 of 2K

Institutions

420

1–8 of 420

Venues

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
51 publications · 3.5K citations
28
h-index
IEEE Transactions on Electron Devices
18 publications · 2K citations
16
h-index
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
21 publications · 583 citations
14
h-index
Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design
ICCAD · 10 publications · 415 citations
10
h-index
IEEE Transactions on Computers
10 publications · 427 citations
10
h-index

1–5