Concepedia

Interconnect Delay Modeling

Interconnect Delay Modeling is a computational methodology within electronic design automation that characterizes signal propagation delay through on-chip interconnects by analytically relating physical and electrical properties of interconnect fabrics to timing performance in CMOS circuits.

588

Publications

27.4K

Citations

1.2K

Authors

315

Institutions

Publications per year

2017–2026

45

Parents

Publications

588

The future of wires

R. Ho, Mark Horowitz · Proceedings of the IEEE · 2001 · 1.4K citations

, , +15

GARNET: A detailed on-chip network model inside a full-system simulator

Niket Agarwal, Tushar Krishna, Li-Shiuan Peh et al. · 2009 · 759 citations · Full text

, , +17

Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs

T. Sakurai · IEEE Transactions on Electron Devices · 1993 · 603 citations

, , +17

Optimal interconnection circuits for VLSI

H. B. Bakoglu, J.D. Meindl · IEEE Transactions on Electron Devices · 1985 · 435 citations

, , +17

A thermal-driven floorplanning algorithm for 3D ICs

Jie Wei, Yan Zhang · 2005 · 431 citations

, , +16

1–5 of 588

Authors

1.2K

  1. AB
    Andrew B. Kahng

    University of California San Diego, United States

    20 publications · 1.1K citations

    17

    h-index

  2. LT
    Lawrence T. Pileggi

    Carnegie Mellon University, United States

    16 publications · 1.1K citations

    14

    h-index

  3. KB
    Kaustav Banerjee

    University of California, Santa Barbara, United States

    14 publications · 1.5K citations

    14

    h-index

  4. BK
    Brajesh Kumar Kaushik

    Indian Institute of Technology Roorkee, India

    16 publications · 633 citations

    14

    h-index

  5. MK
    Manoj Kumar Majumder

    Indian Institute of Technology Roorkee, India

    15 publications · 585 citations

    13

    h-index

1–5 of 1.2K

Institutions

315

  1. The University of Texas at Austin

    Austin, United States

    22 h-index

    63 publications

    3.3K citations

  2. Carnegie Mellon University

    Pittsburgh, United States

    20 h-index

    60 publications

    3.9K citations

  3. University of California, Los Angeles

    Los Angeles, United States

    19 h-index

    61 publications

    3.9K citations

  4. Stanford University

    Stanford, United States

    17 h-index

    47 publications

    5.8K citations

  5. University of California, Berkeley

    Berkeley, United States

    17 h-index

    43 publications

    1.4K citations

  6. Indian Institute of Technology Roorkee

    Roorkee, India

    16 h-index

    53 publications

    2K citations

  7. Georgia Institute of Technology

    Atlanta, United States

    15 h-index

    62 publications

    2.9K citations

  8. IBM (United States)

    Armonk, United States

    14 h-index

    30 publications

    1.5K citations

1–8 of 315

Venues

  1. 23

    h-index

  2. IEEE Transactions on Electron Devices

    25 publications · 3.4K citations

    21

    h-index

  3. 18

    h-index

  4. IEEE Transactions on Nanotechnology

    11 publications · 540 citations

    11

    h-index

  5. IEEE Journal of Solid-State Circuits

    9 publications · 393 citations

    9

    h-index

1–5