Interconnect Delay Analysis

Interconnect Delay Analysis is a computational modeling technique in electronic design automation that characterizes the signal propagation delay along interconnects in integrated circuits by accounting for parasitic resistance, capacitance, and inductance, thereby distinguishing it from gate-delay-centric timing analysis methods.

408

Publications

21K

Citations

835

Authors

228

Institutions

Publications per year

2017–2026

28

Authors

835

  1. AB
    Andrew B. Kahng

    University of California San Diego, United States

    15 publications · 836 citations

    15

    h-index

  2. KB
    Kaustav Banerjee

    University of California, Santa Barbara, United States

    13 publications · 1.2K citations

    13

    h-index

  3. BK
    Brajesh Kumar Kaushik

    Indian Institute of Technology Roorkee, India

    14 publications · 568 citations

    13

    h-index

  4. MK
    Manoj Kumar Majumder

    Indian Institute of Technology Roorkee, India

    13 publications · 540 citations

    12

    h-index

  5. LT
    Lawrence T. Pileggi

    Carnegie Mellon University, United States

    12 publications · 768 citations

    11

    h-index

1–5 of 835

Venues

  1. 16

    h-index

  2. 14

    h-index

  3. IEEE Transactions on Electron Devices

    16 publications · 2.2K citations

    14

    h-index

  4. IEEE Transactions on Nanotechnology

    13 publications · 577 citations

    13

    h-index

  5. IEEE Journal of Solid-State Circuits

    8 publications · 483 citations

    8

    h-index

1–5