Interconnect Delay Analysis
Interconnect Delay Analysis is a computational modeling technique in electronic design automation that characterizes the signal propagation delay along interconnects in integrated circuits by accounting for parasitic resistance, capacitance, and inductance, thereby distinguishing it from gate-delay-centric timing analysis methods.
408
Publications
21K
Citations
835
Authors
228
Institutions
Publications per year
2017–2026
28
Parents
408
R. Ho, Mark Horowitz · Proceedings of the IEEE · 2001 · 1.4K citations
Interconnect scaling-the real limiter to high performance ULSI
M. Bohr · 2002 · 549 citations
1–5 of 408
835
15
h-index
University of California, Santa Barbara, United States
13 publications · 1.2K citations
13
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13
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12
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11
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1–5 of 835
228
IBM Research - Austin
Austin, United States
18 h-index
41 publications
2.3K citations
Carnegie Mellon University
Pittsburgh, United States
17 h-index
44 publications
2.8K citations
Stanford University
Stanford, United States
17 h-index
38 publications
4.7K citations
University of California, Los Angeles
Los Angeles, United States
17 h-index
45 publications
2.3K citations
The University of Texas at Austin
Austin, United States
15 h-index
37 publications
2.3K citations

Indian Institute of Technology Roorkee
Roorkee, India
15 h-index
50 publications
1.9K citations
University of California, Berkeley
Berkeley, United States
14 h-index
31 publications
1.3K citations
IBM (United States)
Armonk, United States
14 h-index
46 publications
6.3K citations
1–8 of 228
23 publications · 1.7K citations
16
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17 publications · 777 citations
14
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16 publications · 2.2K citations
14
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13 publications · 577 citations
13
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8 publications · 483 citations
8
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1–5