2002 · 274 citations · 24 references
EngineeringComputer EngineeringComputer ScienceEmbedded SystemsHardware-software Co-designSystem-on-chip DesignBuilt-in Self-testComputer-based TestingData CompressionDesign For TestabilityProcessor Core DesignTestbenchesEmbedded TestPartial Scan DesignScan Chain DesignScan Chain TestingStorageTest CompressionTest Data ManagementTest Data Reduction
The paper proposes a novel test vector compression/decompression technique to reduce the amount of test data that must be stored on a tester and transferred to each core when testing a core‑based design. The method employs minimal on‑chip circuitry to store compressed test vectors in tester memory, transfer them to the chip, decompress them losslessly, and apply them, thereby reducing storage and transfer size. This approach lowers tester storage requirements and cuts overall test time for data transfer at a fixed bandwidth.
A novel test vector compression/decompression technique is proposed for reducing the amount of test data that must be stored on a tester and transferred to each core when testing a core-based design. A small amount of on-chip circuitry is used to reduce both the test storage and test time required for testing a core-based design. The fully specified test vectors provided by the core vendor are stored in compressed form in the tester memory and transferred to the chip where they are decompressed and applied to the core (the compression is lossless). Instead of having to transfer each entire test vector from the tester to the core, a smaller amount of compressed data is transferred instead. This reduces the amount of test data that must be stored on the tester and hence reduces the total amount of test time required for transferring the data with a given test data bandwidth.
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Combinational profiles of sequential benchmark circuits
F. Brglez, D. Bryan, Krzysztof Koźmiński · 2003 · 2.1K citations
LFSR-coded test patterns for scan designs
B. Koenemann · Medical Entomology and Zoology · 1991 · 510 citations