Low-Cost Through-hole Electrode Interconnection for 3D-SiP Using Room-temperature Bonding

Abstract

To verify the operation of three-dimensional SiP with through-hole electrode interconnections, we manufactured a prototype of a 3D-SiP sample composed of a MCU, an interposer, and a synchronous DRAM (SDRAM) chip using a proposed mechanical caulking operation. A new electrode design of LSI for through-hole electrode interconnection is important for establishing a stable mass-production process. By using this technology, the package thickness can be 1.0 mm or less even in ten-chip layers, compared with two-chip layers using wire bonding, which are approximately 1.25-mm thick