Future system-on-silicon LSI chips

TLDR

The rise of system‑on‑silicon LSI chips has driven a growing need for wiring connectivity, and simply adding metal layers will not keep pace as device sizes shrink. The authors propose a novel three‑dimensional integration technology to address the impending wiring connectivity crisis. Their approach stacks multiple chip layers in 3D LSI chips or MCMs, creating over 10^5 vertical interconnections per chip. This architecture markedly boosts wiring connectivity while shortening long interconnections.

Abstract

The development of system-on-silicon large-scale integration (LSI) devices has significantly influenced the demand for higher wiring connectivity within LSI chips. Currently, increasing the number of metal layers in a multilevel metallization as the device size decreases increases wiring connectivity. In the future, however, designers will have difficulty catching up with the rising demand for higher wiring connectivity by merely increasing the number of metal layers. We propose a new three-dimensional integration technology to overcome future wiring connectivity crises. In our solution, several vertically stacked chip layers in 3D LSI chips or 3D multichip modules (MCMs) are fabricated using our new integration technology. More than 10/sup 5/ interconnections per chip form in a vertical direction in these 3D LSI chips or 3D MCMs. Consequently, we can dramatically increase wiring connectivity while reducing the number of long interconnections.