On the Electron and Hole Tunneling in a $ \hbox{HfO}_{2}$ Gate Stack With Extreme Interfacial-Layer Scaling

Takashi Ando, Ninad D. Sathaye, K. V. R. M. Murali, E. Cartier

IEEE Electron Device Letters · 2011 · 30 citations · 13 references

Concepts

Abstract

With decreasing SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interfacial-layer (IL) thickness, gate currents in SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dual-layer gate stacks are observed to undergo drastic changes. For an IL thickness below 3 Å, a transition from hole-current-dominated transport to electron-current-dominated transport is observed near operating bias conditions in p-channel field-effect transistors. A tunneling simulation based on the transfer-matrix approach suggests that the band offsets for the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layers are reduced in the submonolayer IL regime ( <; 3 Å), promoting the transition in the conduction mechanism.

References

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