IEEE Transactions on Nuclear Science · 2009 · 30 citations · 31 references
EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice CharacterizationDevice ModelingDevice SimulationIntegrated Circuit DesignIntegrated Circuit DevicesCmos Logic CircuitsCmos Logic DesignNumerical Device SimulationPhysics-based Device ModelingSilicon-on-insulator CmosSilicon-on-insulator TechnologySingle Event EffectsTransient Device Modeling
An analytical model is developed to calculate the single-event transient (SET) pulse widths in advanced silicon-on-insulator (SOI) CMOS logic. Waveform analysis reveals that the width of the pulses is large enough to exhibit rail-to-rail trapezoidal waveforms, which are a typical shape for SET pulses in SOI CMOS logic irradiated by ions hitting the center of MOS gates at normal incidence, consisting of two time components. Based on their physical mechanisms, they are modeled as functions of the irradiation and device parameters. The widths and their trends predicted by the model are in good agreement with numerical device simulations and pulsed-laser experimental results.
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