Modeling the effect of technology trends on the soft error rate of combinational logic

TLDR

The study investigates how technology scaling and microarchitectural trends affect soft‑error rates in CMOS memory and logic circuits, and introduces a validated end‑to‑end model for computing SER in current and future microprocessor‑style designs. The model incorporates electrical and latching‑window masking effects and quantifies neutron‑induced SER in SRAM, latches, and logic across 600 nm–50 nm feature sizes and 16–6 fO4 inverter‑delay clock periods. The model predicts a nine‑order‑of‑magnitude rise in logic‑chip SER from 1992 to 2011, reaching parity with unprotected memory, underscoring the need for designers to mitigate soft‑error risks in future logic circuits.

Abstract

This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latching-window masking, which inhibit soft errors in combinational logic. We quantify the SER due to high-energy neutrons in SRAM cells, latches, and logic circuits for feature sizes from 600 nm to 50 nm and clock periods from 16 to 6 fan-out-of-4 inverter delays. Our model predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SER per chip of unprotected memory elements. Our result emphasizes that computer system designers must address the risks of soft errors in logic circuits for future designs.