Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS

Abstract

We activated source/drain junctions of CMOS by simply replacing RTA in the conventional production flow by non-melt laser spike annealing (LSA). We did not form any additional layers unlike the conventional laser annealing. The 50-nm gate CMOS devices thus formed had overwhelmingly better Vth roll-offs and larger drain currents compared to those by RTA. We found that the LSA-devices without offset spacers had better performance than those with offset spacers, and that the optimization of the overlap length between the gate and source/drain extensions was important due to the minimal lateral diffusion during the sub-millisecond annealing of LSA.