IEEE Transactions on Electron Devices · 2013 · 32 citations · 27 references
EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice ModelingDevice SimulationIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsNanowiresAnalytical ModelsCapacitance ModelingLayout Parasitics ModelingMetal-oxide-semiconductor Field-effect Transistor ModelingNanowire DevicesNanowire Field-effect TransistorsNanowire TransistorsParasitic Element Modeling
In this paper, the analytical models of parasitic resistance and capacitance of vertical nanowire (VNW) FET are presented, considering device structural asymmetry. These models are then used to analyze the effect of channel, source-drain extension lengths, and nanowire diameter on device and VNW CMOS performance for 15 nm node. We find that the asymmetry in structure (between top and bottom electrodes) leads to asymmetric parasitic resistances and capacitances that play an important role in determining the circuit delays. Thus our models help to quantify the role of parasitics on VNW device and CMOS performance having device asymmetry. Further, these parasitic models have high potential for use in developing a compact model of a complete device for VNW circuit simulations.
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The effective drive current in CMOS inverters
Mulun Na, E. Nowak, Wilfried Haensch et al. · 2003 · 238 citations
Engineering, Computer Engineering, Electrical Engineering +17