IEEE Journal of Solid-State Circuits · 1982 · 32 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignHigh-frequency Semiconductor DevicesIntegrated Circuit DesignLow-power Digital Circuit DesignParallel ArchitecturesTiming AnalysisGate Delay ModelingHigh-speed Circuit DesignHigh-speed Cmos DesignLow-power MultipliersMultiplier DesignMultipliersSignal Propagation Delay
Multiplication is frequently the speed-limiting function in digital signal processing systems. High-speed hardware multiplier ICs can therefore greatly enhance the throughput and bandwidth of many digital systems. In this paper, the design, fabrication, and performance of GaAs parallel multipliers are discussed. The largest of these circuits, an 8/spl times/8 bit multiplier, has 1008 gates, and is by far the most complex GaAs IC demonstrated today. This multiplier forms the 16 bit product of two 8 bit input numbers in 5.25 ns. This corresponds to an equivalent gate propagation delay of 150 ps/gate. The power dissipation ranges between 0.6-2 mW/gate.
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R.H. Dennard, F.H. Gaensslen, E.J. Walker et al. · IEEE Transactions on Electron Devices · 1979 · 77 citations
Engineering, Computer Engineering, Electrical Engineering +14
The prospects for ultrahigh-speed VLSI GaAs digital logic
R.C. Eden, B.M. Welch, R. Zucca et al. · IEEE Journal of Solid-State Circuits · 1979 · 54 citations
Engineering, Computer Engineering, Electrical Engineering +17
Reliability Study of GaAs MESFET's
Takashi Irie, I. Nagasako, H. Kohzu et al. · IEEE Transactions on Microwave Theory and Techniques · 1976 · 38 citations