IEEE Transactions on Computers · 1984 · 225 citations · 13 references
ComputingComputer EngineeringComputer ScienceFault-tolerant ComputingTest ConstructionTest DevelopmentBuilt-in Self-testComputer-based TestingDesign For TestabilityFault DetectionSoftware TestingVerificationAutomated Test GenerationAutomatic Test Pattern GenerationDigital Circuit Self-testingFault CoverageFault Coverage AnalysisFault SimulationSelf-test ArchitectureTest Generation
The paper proposes a new test pattern generation approach tailored for self‑test. The method generates test patterns algorithmically without fault simulation or modeling, using either software or hardware. The approach yields faster computation, produces more patterns, and achieves higher fault coverage than standard ATPG.
A new approach to test pattern generation which is particularly suitable for self-test is described. Required computation time is much less than for present day automatic test pattern generation (ATPG) programs. Fault simulation or fault modeling is not required. More patterns may be obtained than from standard ATPG programs. However, fault coverage is much higher—all irredundant multiple as well as single stuck faults are detected. The test patterns are easily generated algorithmically either by program or hardware.
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Design for testability—A survey
T.W. Williams, Kenneth P. Parker · Proceedings of the IEEE · 1983 · 393 citations
J. Savir, Gary S. Ditlow, Paul H. Bardell · IEEE Transactions on Computers · 1984 · 282 citations
McCluskey, Bozorgui-Nesbat · IEEE Transactions on Computers · 1981 · 225 citations