Improvement of asymmetrical characteristics in submicron CMOS devices

Abstract

Abstract In the substrate current characteristics and the drain current characteristics in a submicron nMOSFET with an LDD structure, the problem of asymmetry caused by ion implantation occurs if the measurement is done with the source and drain interchanged. It is found also that significant asymmetry appears in the subthreshold current characteristics (threshold voltage) in a submicron pMOSFET with EPS (efficient punchthrough stops). By introducing the four‐step implantation method as a technique to form LDD and EPS regions, an attempt was made to improve asymmetry. By this method, symmetric electrical characteristics are obtained without changing the conventional process and without reducing the throughput. Further, the unbalance of the threshold voltages between the pair transistors was measured because they have the greatest effect on the sensitivity of the sense amplifier important in the VLSIDRAM. It was found that the four‐step implantation method is extremely effective for suppressing the asymmetry without changing the circuit design.