IEEE Electron Device Letters · 1995 · 28 citations · 8 references
EngineeringElectrical EngineeringElectronic MaterialsMicroelectronicsSemiconductor DevicesCarrier TransportCurrent-voltage CharacteristicsDevice CharacterizationDevice ModelingDevice SimulationMetal-oxide-semiconductor Field-effect TransistorsCapacitive CouplingDeep DepletionElectron Impact IonizationFully Depleted Silicon-on-insulator TransistorsIonizationSilicon-on-insulator CmosSilicon-on-insulator TechnologyTransient Device Modeling
The transient operation of partially depleted (PD) Silicon-On-Insulator (SOI) NMOSFET's is investigated, based on two-dimensional numerical simulations. The studied devices have a gate length of 0.2 μm and a floating body. They are designed for a supply voltage of 2 V. In the case of gate transient, we show that the body voltage is more influenced by the capacitive coupling with the gate electrode than the impact ionization current. Further, we demonstrate, for the first time, that the anomalous subthreshold slope, that exists in a DC static transfer I-V curve, does not exist in fast transient mode because the minimum time constant for body charging by impact ionization current is on the order of 3 ns in such devices.
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A room temperature 0.1 μm CMOS on SOI
G. Shahidi, Clint Anderson, B.A. Chappell et al. · IEEE Transactions on Electron Devices · 1994 · 80 citations
Engineering, Computer Engineering, Electrical Engineering +16