B.A. Chappell

A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture

T.I. Chappell, B.A. Chappell, S.E. Schuster et al. · IEEE Journal of Solid-State Circuits · 1991 · 122 citations

Pipelined Architecture, Engineering, Vlsi Design +17

A room temperature 0.1 μm CMOS on SOI

G. Shahidi, Clint Anderson, B.A. Chappell et al. · IEEE Transactions on Electron Devices · 1994 · 80 citations

Low-power Electronics, Advanced 0.1, Electrical Engineering +10

Fast CMOS ECL receivers with 100-mV worst-case sensitivity

B.A. Chappell, T.I. Chappell, S.E. Schuster et al. · IEEE Journal of Solid-State Circuits · 1988 · 59 citations

Hardware Security, Electrical Engineering, Engineering +15

CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications

G. Shahidi, J.D. Warnock, J.H. Comfort et al. · IBM Journal of Research and Development · 1995 · 43 citations

Low-power Electronics, Electrical Engineering, Cmos Scaling +14

SOI for a 1-volt CMOS technology and application to a 512 Kb SRAM with 3.5 ns access time

G. Shahidi, T.H. Ning, T.I. Chappell et al. · 2002 · 39 citations

Low-power Electronics, Electrical Engineering, Engineering +14