A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture

Abstract

The authors describe a 512 K CMOS static RAM (SRAM) with emitter-coupled-logic (ECL) interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random READ/WRITE operations. The CMOS technology and the physical organization of the chip are briefly discussed, and the pipelined architecture of the chip is described. Detailed measurements of internal chip waveforms demonstrating 2-ns cycle time operation are presented. The impact of wire RC delays on performance is discussed. Circuit examples that demonstrate the implementation of the pipelined architecture are included. Measurements of operating margins, access time, and cycle time are outlined.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>