T.I. Chappell - Concepedia

Author

T.I. Chappell

IBM Research - Thomas J. Watson Research Center

Also Known As

T. CHAPPELL, T. Chappell, T. I. Chappell, T.I. Chappell, Terry I. Chappell

Publications

974

Citations

H-Index

Concepts

All Affiliations

IBM Research - Thomas J. Watson Research Center IBM (United States)University of California, Berkeley

About

T.I. Chappell is an author at IBM Research - Thomas J. Watson Research Center specializing in engineering, microelectronics, and applied physics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	16	19	935
2	Applied Physics	10	11	569
3	Computer Engineering	9	9	409
4	Natural Sciences	2	2	115
5	Education	1	1	23

T.I. Chappell

Publications

935

Citations

H-Index

Page 1

	Year	Citations
Unpinned (100) GaAs surfaces in air using photochemistry S. D. Offsey, J. M. Woodall, A.C. Warren, Applied Physics Letters SemiconductorsSurface Fermi LevelElectronic DevicesEngineeringInsulator/gaas Interface	1986	211
A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture T.I. Chappell, B.A. Chappell, S.E. Schuster, IEEE Journal of Solid-State Circuits Pipelined ArchitectureEngineeringVlsi DesignMemory DesignComputer Architecture	1991	122
The analysis of exponential and nonexponential transients in deep-level transient spectroscopy P. D. Kirchner, W. J. Schaff, G.N. Maracas, Journal of Applied Physics Transient GratingEngineeringMeasurementComputerized Waveform CaptureTimefrequency Analysis	1981	99
A room temperature 0.1 μm CMOS on SOI G. Shahidi, Clint Anderson, B.A. Chappell, IEEE Transactions on Electron Devices Low-power ElectronicsAdvanced 0.1Electrical EngineeringμM CmosEngineering	1994	80
Fast CMOS ECL receivers with 100-mV worst-case sensitivity B.A. Chappell, T.I. Chappell, S.E. Schuster, IEEE Journal of Solid-State Circuits Hardware SecurityElectrical EngineeringEngineeringCircuit SystemCircuit Design	1988	59
A 0.18-μm CMOS IA-32 processor with a 4-GHz integer execution unit G. Hinton, Mike Upton, Dave Sager, IEEE Journal of Solid-State Circuits Hardware SecuritySystem On ChipCo-processorsEngineeringHardware Acceleration	2001	50
CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications G. Shahidi, J.D. Warnock, J.H. Comfort, IBM Journal of Research and Development Low-power ElectronicsElectrical EngineeringCmos ScalingEngineeringVlsi Design	1995	43
The V-groove multijunction solar cell T.I. Chappell IEEE Transactions on Electron Devices Electrical EngineeringEngineeringEnergy EfficiencyEnergy ConversionOrganic Solar Cell	1979	43
SOI for a 1-volt CMOS technology and application to a 512 Kb SRAM with 3.5 ns access time G. Shahidi, T.H. Ning, T.I. Chappell, Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignHigh-speed Electronics	2002	39
A 2ns Cycle, 4ns Access 512kb CMOS ECL SRAM T.I. Chappell, B.A. Chappell, S.E. Schuster, Hardware SecurityEngineeringVlsi DesignMemory DesignCmos Ecl Sram	1991	30

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