IEEE Transactions on Electron Devices · 2001 · 10 citations · 10 references
EngineeringElectrical EngineeringMaterials ScienceMicroelectronicsSemiconductor DevicesSemiconductor MaterialsIntegrated Circuit DevicesIntegrated Circuit FabricationMetal-oxide-semiconductor Field-effect TransistorsOxide SemiconductorsSemiconductor Device MaterialsSemiconductor InterfacesCmos Fabrication ProcessesDamascene ProcessGate Oxide InterfacesGate Oxide ReliabilityGate OxidesMetal Gate ElectrodesMetal GatesOxide Reliability
Full chemical mechanical polishing (CMP) process integration of a W/TiN damascene metal gate has been optimized and is demonstrated to be compatible with ULSI circuit fabrication. Highly uniform and reliable electrical characteristics are achieved for widely ranged MOS pattern structures (from 0.1-/spl mu/m gate transistors up to 0.6-mm/sup 2/ capacitors). CVD TiN film as a damascene gate electrode shows excellent properties for MOS performances and gate oxide integrity even on ultrathin gate oxide (2-nm SiO/sub 2/).
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High performance metal gate MOSFETs fabricated by CMP for 0.1 μm regime
A. Yagishita, Tomohiro Saito, K. Nakajima et al. · 2002 · 34 citations