High performance damascene metal gate MOSFETs for 0.1 μm regime

TLDR

The authors developed a damascene gate process to integrate metal gates and high‑k insulators into MOSFETs while reducing plasma damage to the gate dielectric. The process forms gate insulators and electrodes after ion implantation and high‑temperature annealing, then deposits metal (W/TiN or Al/TiN) into grooves and planarizes them by chemical‑mechanical polishing on an 8‑inch wafer. This approach enables gate formation at 450 °C, minimizes damage, produces low‑sheet‑resistivity, depletion‑free metal gates with superior oxide integrity, and yields high‑performance transistors.

Abstract

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (/spl sim/1000/spl deg/C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450/spl deg/C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO/sub 2/ or Ta/sub 2/O/sub 5/ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance.