Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI

T. Morimoto, T. Ohguro, H.S. Momose, +9

IEEE Transactions on Electron Devices

EngineeringVlsi DesignOptoelectronic DevicesIntegrated CircuitsSilicon On Insulator +16

10–15 nm Ultrashallow Junction Formation by Flash-Lamp Annealing

Takayuki Ito, Toshihiko Iinuma, Atsushi Murakoshi, +9

Japanese Journal of Applied Physics

Materials ScienceSemiconductor TechnologyElectrical EngineeringPhotoluminescenceEngineering +9

Improvement of threshold voltage deviation in damascene metal gate transistors

A. Yagishita, Tomohiro Saito, K. Nakajima, +6

IEEE Transactions on Electron Devices

Device ModelingMaterials ScienceElectrical EngineeringMaterials EngineeringEngineering +8

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

K. Okano, T. Izumida, H. Kawasaki, +19

Electrical EngineeringBulk Silicon SubstrateEngineeringWafer Scale ProcessingAdvanced Packaging (Semiconductors) +7

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

S. Inaba, K. Okano, Shôichi Matsuda, +22

IEEE Transactions on Electron Devices

Low-power ElectronicsNitrogen ConcentrationElectrical EngineeringEngineeringHigh Performance 35 +10

Low-temperature redistribution of As in Si during Pd2Si formation

Iwao Ohdomari, K. N. Tu, K. Suguro, +3

Applied Physics Letters

Materials ScienceSemiconductor TechnologyIon ImplantationEngineeringPhysics +11

High-Performance FinFET with Dopant-Segregated Schottky Source/Drain

A. Kaneko, A. Yagishita, K. Yahashi, +18

Low-power ElectronicsPropagation Delay TimeElectrical EngineeringEngineeringNanoelectronics +8

Self-aligned passivation on copper interconnection durability against oxidizing ambient annealing

Hitoshi Itow, Yasushi Nakasaki, G. Minamihaba, +2

Applied Physics Letters

Self-aligned NiobiumEngineeringOxidation ResistanceChemistryCopper Interconnection Durability +15

Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

Hikaru Kawasaki, K. Okano, A. Kaneko, +15

Electrical EngineeringEngineeringVlsi DesignStatic Noise MarginHp32 Nm Node +10

Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension

A. Kaneko, A. Yagishita, K. Yahashi, +15

Electrical EngineeringEngineeringSidewall Transfer ProcessSpacer FormationNanoelectronics +6