High performance metal gate MOSFETs fabricated by CMP for 0.1 μm regime

Abstract

We propose a plasma and thermal damage-free gate process named the "Damascene gate process" where CMP (Chemical Mechanical Polishing) is used in forming the gate structure. By using this process, fully planarized high performance metal (W/TiN or Al/TiN) gate transistors with pure SiO/sub 2/ or Ta/sub 2/O/sub 5/ as gate insulators were fabricated with very uniform and highly reliable electrical characteristics. Therefore, this technology is useful in fabricating 0.1 /spl mu/m MOSFETs and beyond.