IEEE Journal of Solid-State Circuits · 1988 · 15 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignBuilt-in Self-testClock ManagementCmos Circuit DesignIntegrated Circuit DesignLow-power Digital Circuit DesignTiming AnalysisClocking ArchitectureClocking SchemesHigh-speed Cmos DesignLow-power Memory CircuitsMemory Circuit DesignStatic Cmos CircuitsStatic Power DissipationStatic Random-access Memory Design
An experimental 11-ns 8 K*18 static RAM fabricated in a 1.2- mu m CMOS technology with 0.5- mu m channel lengths is described. Novel interface circuits allow full TTL-level compatibility with a scaled 3.6-V V/sub dd/. Synchronous clocking and automatic restore operations were implemented to realize high-speed access and a fast cycle data rate of 8 ns. Double-word-line architecture and a pulsed word-line technique reduce power dissipation. Other features include on-chip test circuitry that increases tester timing accuracy and word-line redundancy. The design uses a single-poly, double-metal technology with a CMOS six-transistor cell of 235 mu m/sup 2/ to yield a chip size of 60 mm/sup 2/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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S.E. Schuster, B.A. Chappell, V. Di Lonardo et al. · IEEE Journal of Solid-State Circuits · 1984 · 13 citations
Engineering, Computer Engineering, Electrical Engineering +13