John Gabric

An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage

Harold Pilo, J.C. Barwin, G. Braceras et al. · 2006 · 112 citations

Engineering, Computer Engineering, Electrical Engineering +17

Design considerations for MRAM

T. Maffitt, J. DeBrosse, John Gabric et al. · IBM Journal of Research and Development · 2006 · 83 citations

Natural Sciences, Electrical Engineering, Materials Science +17

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

Harold Pilo, Igor Arsovski, Kevin Batson et al. · IEEE Journal of Solid-State Circuits · 2011 · 79 citations

Engineering, Computer Engineering, Electrical Engineering +14

A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements

Harold Pilo, Igor Arsovski, Kevin Batson et al. · 2011 · 43 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management

Harold Pilo, Vinod Ramadurai, G. Braceras et al. · 2008 · 27 citations

Engineering, Computer Engineering, Electrical Engineering +17