An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage

Abstract

This paper describes a 32Mb SRAM that has been designed and fabricated in a 65nm low-power CMOS technology. The design has also been migrated to 45nm bulk and SOI technologies. The 68mm die features read and write-assist circuit techniques that expand the operating voltage range and improve manufacturability across technology platforms