G. Braceras

An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage

Harold Pilo, Charlie Barwin, G. Braceras et al. · IEEE Journal of Solid-State Circuits · 2007 · 136 citations

Engineering, Vlsi Design, Computer Architecture +16

An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage

Harold Pilo, J.C. Barwin, G. Braceras et al. · 2006 · 112 citations

Low-power Electronics, Low-power Cmos Technology, Electrical Engineering +12

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

Harold Pilo, Igor Arsovski, Kevin Batson et al. · IEEE Journal of Solid-State Circuits · 2011 · 79 citations

Non-volatile Memory, Engineering, Vlsi Design +19

Impact of circuit assist methods on margin and performance in 6T SRAM

R. Mann, Satyanand Nalam, Sudhanshu Khanna et al. · Solid-State Electronics · 2010 · 50 citations

Electrical Engineering, Engineering, Vlsi Design +7

A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements

Harold Pilo, Igor Arsovski, Kevin Batson et al. · 2011 · 43 citations

Non-volatile Memory, Electrical Engineering, Bc Area +13