S. Lamphier

An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage

Harold Pilo, J.C. Barwin, G. Braceras et al. · 2006 · 112 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction

Harold Pilo, C. A. Adams, Igor Arsovski et al. · 2013 · 32 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface

Harold Pilo, D. Anand, J. Barth et al. · IEEE Journal of Solid-State Circuits · 2003 · 18 citations

Engineering, Computer Engineering, Electrical Engineering +17

An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin

Harold Pilo, Andrew J. Allen, J. Covino et al. · IEEE Journal of Solid-State Circuits · 2000 · 13 citations

Engineering, Computer Engineering, Electrical Engineering +12

A 300 MHz, 3.3 V 1 Mb SRAM fabricated in a 0.5 μm CMOS process

Harold Pilo, S. Lamphier, Fred Towler et al. · 2002 · 12 citations

Engineering, Computer Engineering, Electrical Engineering +17