Self-aligned InAs/Al<inf>0.45</inf>Ga<inf>0.55</inf>Sb vertical tunnel FETs

Abstract

Tunnel field-effect transistors (TFETs) are under intense investigation for low-power applications because of their potential for extremely low subthreshold swing (SS) and low off-state leakage [1]. III–V semiconductors with small effective mass and near broken band alignment are considered to be ideal for TFETs in that they promise high on-current and I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> /I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> ratios [2–3]. In this paper, we report the first demonstration of an InAs/Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.45</inf> Ga <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.55</inf> Sb heterojunction TFETs fabricated using an optical-lithography-only, self-aligned process and also investigate the effects limiting the InAs/Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.45</inf> Ga <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.55</inf> Sb TFET performance.