IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2014 · 72 citations · 36 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignDevice CharacterizationDevice ModelingDevice SimulationIntegrated Circuit DesignLow-power Digital Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsField-effect Transistor SimulationLeakage CurrentLeakage Current ModelingLeakage Current ReductionMetal-oxide-semiconductor Field-effect Transistor ModelingMosfet ModelingTunneling Field-effect TransistorsUltra-low-voltage Circuit Design
This paper and the companion work present the results of a comparative study between the tunnel-FETs (TFETs) and conventional MOSFETs for ultralow power digital circuits targeting a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> below 500 mV. For this purpose, we employed numerical TCAD simulations, as well as mixed device-circuit and lookup-table simulations using either the SENTAURUS or the Verilog-A environment. In particular, in this paper, we explore the device-circuit interaction in n- and p-type TFETs, and propose a design leading to a good tradeoff between the current leakage and transistor imbalance at ultralow V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , as required in ultralow voltage systems. Then, we systematically compare the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> , I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> , effective capacitance, OFF-state and ON-state stacking factors for TFETs, SOI, and bulk MOSFETs in a wide range of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> . These results allow us to infer preliminary indications about the amenability for an aggressive voltage scaling of TFETs compared with MOSFETs, which will be further developed in the companion paper. We also report simulation results for the sensitivity of the transistors to the variation of some key device parameters. Even these process variation results set the stage for a more thorough investigation addressed in the companion paper about the limits imposed by process variability to voltage scaling for either TFETs or MOSFETs circuits.
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A 90-nm logic technology featuring strained-silicon
Scott E. Thompson, M Armstrong, C. Auth et al. · IEEE Transactions on Electron Devices · 2004 · 666 citations