Comparative Analysis of Process Variation Impact on Flip-Flop Power-Performance

Abstract

This paper presents an analysis of process variation impact on four flip-flops in 90-nm CMOS. The analyzed flip-flops are compared for required delay overhead and timing uncertainty. The analysis shows that the ±2σ delay variation for two standard master-slave flip-flops is 30% due to random process variation. Pulsed and sense-amplifier based flip-flops suffer 2-2.5× higher delay variation compared to the master-slave flip-flops. Further, the delay variation in the master-slave flip-flops is 2.7× larger than the delay variation in a 5-stage inverter-chain. Therefore, the process variation impact on flip-flops will dominate over the delay spread of the logic.