Timing Overhead Analysis
Timing Overhead Analysis is a methodological framework within low-power VLSI design that specifically quantifies the performance degradation introduced by clock gating structures through the evaluation of delay, skew, and jitter impacts on critical path timing.
98
Publications
3K
Citations
256
Authors
104
Institutions
Publications per year
2017–2026
12
Parents
98
Too much delay fault coverage is a bad thing
Jeff Rearick · 2002 · 264 citations
Engineering, Computer Engineering, Electrical Engineering +17
CheCUDA: A Checkpoint/Restart Tool for CUDA Applications
Hiroyuki Takizawa, Katsuto Sato, Kazuhiko Komatsu et al. · 2009 · 87 citations
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104
Intel (United States)
Santa Clara, United States
5 h-index
10 publications
1.2K citations

University of Toronto
Toronto, Canada
5 h-index
12 publications
186 citations
University of Michigan
Ann Arbor, United States
4 h-index
9 publications
443 citations
University of California, Los Angeles
Los Angeles, United States
4 h-index
21 publications
378 citations

University of Waterloo
Waterloo, Canada
4 h-index
8 publications
317 citations
University of Southern California
Los Angeles, United States
3 h-index
5 publications
66 citations
Stanford University
Stanford, United States
3 h-index
5 publications
254 citations
Tokyo Institute of Technology
Tokyo, Japan
2 h-index
2 publications
22 citations
1–8 of 104
4 publications · 75 citations
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3 publications · 51 citations
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3 publications · 144 citations
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Conference · 2 publications · 71 citations
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MICPRO · 2 publications · 34 citations
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