Timing Overhead Analysis

Timing Overhead Analysis is a methodological framework within low-power VLSI design that specifically quantifies the performance degradation introduced by clock gating structures through the evaluation of delay, skew, and jitter impacts on critical path timing.

98

Publications

3K

Citations

256

Authors

104

Institutions

Publications per year

2017–2026

12

Authors

256

  1. CH
    Cody Hao Yu

    University of California, Los Angeles, United States

    3 publications · 54 citations

    3

    h-index

  2. SB
    Swarup Bhunia

    Case Western Reserve University, United States

    3 publications · 35 citations

    3

    h-index

  3. VB
    Vaughn Betz

    University of Toronto, Canada

    3 publications · 60 citations

    3

    h-index

  4. DS
    Dennis Sylvester

    University of Michigan, United States

    3 publications · 146 citations

    3

    h-index

  5. HT
    Hiroyuki Tomiyama

    Ritsumeikan University, Japan

    2 publications · 22 citations

    2

    h-index

1–5 of 256

Venues

  1. 4

    h-index

  2. 3

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  3. IEEE Journal of Solid-State Circuits

    3 publications · 144 citations

    3

    h-index

  4. International Conference on Computer Aided Design

    Conference · 2 publications · 71 citations

    2

    h-index

  5. Microprocessors and Microsystems

    MICPRO · 2 publications · 34 citations

    2

    h-index

1–5