Electrical Overstress/Electrostatic Discharge Symposium · 2010 · 15 citations · 12 references
EngineeringComputer EngineeringElectrical EngineeringDesign AutomationDesign OptimizationMicroelectronicsDesign For TestabilityDesign SimulationDevice CharacterizationDevice ModelingDevice SimulationIntegrated Circuit DesignCircuit SimulationCompact Device ModelingCompact ModelingComputer-aided Design For Integrated CircuitsCorrelationHardware SimulationMetal-oxide-semiconductor Field-effect Transistor ModelingValidation Of Integrated Circuits
We present a new ESD compact modeling methodology using Verilog-A to enable predictive full circuit ESD simulation along with supporting hardware and failure analysis results. We also present a new ESD tool (ESTEEM) to automate the ESD design simulation and optimization flow for circuit designers. Test results show excellent simulation to hardware data correlation.
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