Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices

Abstract

Previous work on electrothermal simulation using network analysis techniques has been of limited use due to the lack of avalanche breakdown modeling capability and the models to efficiently describe the temperature dynamics. Particularly, simulation of electrical overstress (EOS) and electrostatic discharge (ESD), which are important threats to IC reliability, require an accurate description of temperature-dependent device electrical behaviour including breakdown phenomenon. This paper presents electrothermal device models and their implementation in a new circuit-level electrothermal simulator iETSIM. Simulation results for an I/O protection device in an advanced MOS process are presented to demonstrate iETSIM's ability to accurately model device behaviour up to the onset of second breakdown.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>