Validation Of Integrated Circuits

Validation of Integrated Circuits is a systematic process within the development lifecycle of Application-Specific Integrated Circuits that verifies the functional correctness, performance, and reliability of a designed circuit against its intended specifications and real-world operational requirements through simulation, emulation, and testing methodologies.

124

Publications

3.9K

Citations

390

Authors

146

Institutions

Publications per year

2017–2026

12

Authors

390

  1. MB
    M.A. Breuer

    University of Southern California, United States

    4 publications · 115 citations

    4

    h-index

  2. DW
    D.M.H. Walker

    Texas A&M University, United States

    4 publications · 64 citations

    4

    h-index

  3. CG
    Chenjie Gu

    Ningbo University, China

    4 publications · 79 citations

    4

    h-index

  4. XL
    Xin Li

    Carnegie Mellon University, United States

    3 publications · 57 citations

    3

    h-index

  5. AZ
    Avi Ziv

    IBM Research - Haifa, Israel

    3 publications · 125 citations

    3

    h-index

1–5 of 390

Venues

  1. IEEE Design & Test of Computers

    8 publications · 465 citations

    8

    h-index

  2. 3

    h-index

  3. IEEE Design and Test

    3 publications · 113 citations

    3

    h-index

  4. 3

    h-index

  5. 2

    h-index

1–5