2003 · 28 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryLogicMicroelectronicsBuilt-in Self-testCombinational Logic DescriptionDesign For TestabilityDigital Logic DesignLogic SynthesisTiming AnalysisAutomatic Test Pattern GenerationCombinational Logic DesignCombinational Logic SynthesisDesign ValidationGround BounceGround Bounce AnalysisLogic Built-in Self-testTest Generation
Ground bounce in internal circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in internal circuitry is proposed. Based on this model an algorithm for generating test patterns that maximize ground bounce in combinational logic is presented. Our algorithm is also applicable to other test problems such as delay testing in the presence of excessive ground bounce.
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