80nm self-aligned complementary I-MOS using double sidewall spacer and elevated drain structure and its applicability to amplifiers with high linearity

Abstract

We demonstrate an 80nm self-aligned complementary I-MOS for the first time by using double sidewall spacer, elevated drain structure and RTA process. It shows a normal transistor operation with small subthreshold swing which ranges from 5.5 to 12.2mV/dec at room temperature. The n- and p-channel I-MOS had an ON/OFF current of 394.1/0.3/spl mu/A and 355.4/8.9/spl mu/A per /spl mu/m, respectively. We also investigate the effect of L/sub 1/ variation to device characteristics and finally show the feasibility of the I-MOS as an amplifier with high linearity.