Process Variation Tolerance

Process Variation Tolerance is a design-level attribute in near-threshold computing that characterizes a system’s resilience to parametric deviations in manufacturing processes by maintaining correct functionality and performance despite variations in transistor-level electrical properties.

490

Publications

22.3K

Citations

1.6K

Authors

345

Institutions

Publications per year

2017–2026

91

Authors

1.6K

  1. KR
    Kaushik Roy

    Purdue University West Lafayette, United States

    24 publications · 2.2K citations

    20

    h-index

  2. VD
    Vivek De

    Intel (United States), United States

    12 publications · 2.1K citations

    11

    h-index

  3. SB
    Shekhar Borkar

    Intel (United States), United States

    10 publications · 2K citations

    10

    h-index

  4. DB
    David Blaauw

    University of Michigan, United States

    10 publications · 1.3K citations

    10

    h-index

  5. TK
    Tanay Karnik

    Intel (United States), United States

    9 publications · 2K citations

    9

    h-index

1–5 of 1.6K

Venues

  1. IEEE Journal of Solid-State Circuits

    22 publications · 2.6K citations

    20

    h-index

  2. 19

    h-index

  3. 13

    h-index

  4. 11

    h-index

  5. IEEE Transactions on Electron Devices

    11 publications · 626 citations

    10

    h-index

1–5