High-performance CMOS variability in the 65-nm regime and beyond

TLDR

Recent CMOS scaling beyond 90 nm and emerging materials have intensified delay and power variability driven by process, temperature, supply, wear‑out, and usage, altering how tolerance is specified in high‑performance designs. The paper surveys the main contributors to variability in modern CMOS and proposes preferred mitigation strategies. The authors analyze process, device, and circuit responses to systematic and random tolerance components to guide mitigation.

Abstract

Recent changes in CMOS device structures and materials motivated by impending atomistic and quantum-mechanical limitations have profoundly influenced the nature of delay and power variability. Variations in process, temperature, power supply, wear-out, and use history continue to strongly influence delay. The manner in which tolerance is specified and accommodated in high-performance design changes dramatically as CMOS technologies scale beyond a 90-nm minimum lithographic linewidth. In this paper, predominant contributors to variability in new CMOS devices are surveyed, and preferred approaches to mitigate their sources of variability are proposed. Process-, device-, and circuit-level responses to systematic and random components of tolerance are considered. Exploratory, novel structures emerging as evolutionary CMOS replacements are likely to change the nature of variability in the coming generations.