D.J. Pearson

High-performance CMOS variability in the 65-nm regime and beyond

K. Bernstein, D.J. Frank, Anne Gattiker et al. · IBM Journal of Research and Development · 2006 · 552 citations

Engineering, Vlsi Design, Computer Architecture +16

Chemical‐Mechanical Polishing for Fabricating Patterned W Metal Features as Chip Interconnects

F. B. Kaufman, Daniel B. Thompson, R. E. Broadie et al. · Journal of The Electrochemical Society · 1991 · 506 citations

Engineering, Mechanical Engineering, Chip Interconnects +19

Copper interconnection integration and reliability

C.‐K. Hu, B. M. Luther, F. B. Kaufman et al. · Thin Solid Films · 1995 · 222 citations

Reliability, Copper Interconnection Integration, Electrical Engineering +8

High Performance CMOS Variability in the 65nm Regime and Beyond

Sani Nassif, Kerry Bernstein, D.J. Frank et al. · 2007 · 132 citations

Low-power Electronics, Power Consumption, Electrical Engineering +14

Sub-μm, planarized, Nb-AlO<i>x</i>-Nb Josephson process for 125 mm wafers developed in partnership with Si technology

M. B. Ketchen, D.J. Pearson, A. W. Kleinsasser et al. · Applied Physics Letters · 1991 · 107 citations

Superconducting Material, Engineering, Si Technology +17