High Performance CMOS Variability in the 65nm Regime and Beyond

Abstract

This paper has described the performance of CMOS and categorises the variability. The inability to scale the tolerance of multiple electrical parameters along with their nominal value has contributed to a virtual crisis in the ability to improve performance and power consumption in new processes. The continued infusion of new materials and structures provide an illusion of conventional scaling, but assert additional idiosyncrasies as well. New device structures and materials may allow CMOS to scale further, but variability isn't likely to decrease, since smaller devices contain fewer atoms and consequently exhibit less self-averaging. The situation may be improved by removing most of the doping.