A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM

TLDR

Proposes a novel Schmitt‑trigger based differential 10‑transistor SRAM bitcell for subthreshold operation. It employs differential operation, requiring no architectural changes from the conventional 6T cell. The ST‑based 10‑T SRAM achieves a 1.56× higher read SNM at 400 mV, tolerates process variation, operates at 175 mV with 18 % lower leakage and 50 % power savings, retains data down to 150 mV, and demonstrates functional operation at 160 mV in 0.13 µm CMOS.

Abstract

We propose a novel Schmitt trigger (ST) based differential 10-transistor SRAM (static random access memory) bitcell suitable for subthreshold operation. The proposed Schmitt trigger based bitcell achieves 1.56 x higher read static noise margin (SNM) ( Vdd = 400 mV) compared to the conventional 6T cell. The robust Schmitt trigger based memory cell exhibits built-in process variation tolerance that gives tight SNM distribution across the process corners. It utilizes differential operation and hence does not require any architectural changes from the present 6T architecture. At iso-area and iso-read-failure probability the proposed memory bitcell operates at a lower (175 mV) Vdd with 18% reduction in leakage and 50% reduction in read/write power compared to the conventional 6T cell. Simulation results show that the proposed memory bitcell retains data at a supply voltage of 150 mV. Functional SRAM with the proposed memory bitcell is demonstrated at 160 mV in 0.13 mum CMOS technology.