Embedded Die Packaging
Embedded Die Packaging is a chip packaging technology in which a semiconductor die is embedded within a substrate or encapsulation material to enable high-density interconnectivity, improved thermal dissipation, and reduced package footprint compared to conventional surface-mounted die configurations.
93
Publications
4.3K
Citations
431
Authors
87
Institutions
Publications per year
2017–2026
19
Parents
93
Embedded Wafer Level Ball Grid Array (eWLB)
Tyler Meyer, G. Ofner, S. Bradl et al. · 2008 · 236 citations
Engineering, Computer Engineering, Electrical Engineering +16
Embedded wafer level ball grid array (eWLB)
Markus Brunnbauer, E. F�rgut, G. Beer et al. · 2006 · 187 citations
Engineering, Computer Engineering, Electrical Engineering +16
1–5 of 93
431
5
h-index
5
h-index
5
h-index
Fraunhofer Institute for Reliability and Microintegration, Germany
5 publications · 100 citations
5
h-index
Fraunhofer Institute for Reliability and Microintegration, Germany
5 publications · 138 citations
5
h-index
1–5 of 431
87
Institute of Microelectronics
Singapore, Singapore
9 h-index
56 publications
1.6K citations
Infineon Technologies (Germany)
Munich, Germany
7 h-index
32 publications
4.5K citations
Georgia Institute of Technology
Atlanta, United States
7 h-index
42 publications
1.1K citations
Agency for Science, Technology and Research
Singapore, Singapore
6 h-index
49 publications
1.4K citations
Fraunhofer Institute for Reliability and Microintegration
Berlin, Germany
6 h-index
23 publications
626 citations
STATS ChipPAC (Singapore)
Singapore, Singapore
6 h-index
15 publications
599 citations
Intel (United States)
Santa Clara, United States
5 h-index
34 publications
4.5K citations
Technische Universität Berlin
Berlin, Germany
5 h-index
14 publications
336 citations
1–8 of 87
9 publications · 264 citations
9
h-index
7 publications · 652 citations
7
h-index
3 publications · 96 citations
3
h-index
2 publications · 55 citations
2
h-index
1 publications · 19 citations
1
h-index
1–5