D. Jaeger - Concepedia

Author

D. Jaeger

IBM (United States)

Also Known As

D. Jaeger, Daniel J Jaeger, Daniel J. Jaeger, Daniel Jaeger

Publications

506

Citations

H-Index

Concepts

All Affiliations

IBM (United States)Infineon Technologies (Germany)Samsung (South Korea)GlobalFoundries (United States)Toshiba (United States)

About

D. Jaeger is an author at IBM (United States) specializing in engineering, microelectronics, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	470
2	Electrical Engineering	8	8	443
3	Applied Physics	7	7	385
4	Computer Engineering	5	5	389
5	Natural Sciences	1	1	27

D. Jaeger

Publications

470

Citations

H-Index

Page 1

	Year	Citations
A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process X. Chen, S. Samavedam, Vijay Narayanan, Low-power ElectronicsLow Power ApplicationsElectrical EngineeringEngineeringVlsi Design	2008	112
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL P. Chang, C. Ortolland, David Fried, High-performance Soi TechnologyEngineeringVlsi DesignComputer ArchitectureInterconnect (Integrated Circuits)	2012	89
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications Siddarth Krishnan, U. Kwon, N. Moumen, Sige ChannelsLow Power ApplicationsEngineeringVlsi DesignIntegrated Circuits	2011	81
A 7nm CMOS technology platform for mobile and high performance compute application B. Jagannathan, Akihisa Ogino, D. Jaeger, EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsHardware Systems	2017	58
Scaling of 32nm low power SRAM with high-K metal gate Haining Yang, Robert Wong, R. Hasumi, Electrical EngineeringEngineeringVlsi DesignPhysicsTechnology Scaling	2008	49
Uniform Coverage Tool Path Generation for Robotic Surface Finishing of Curved Surfaces Yalun Wen, D. Jaeger, Prabhakar R. Pagilla IEEE Robotics and Automation Letters Robot KinematicsEngineeringMechanical EngineeringField RoboticsRobotic Surface Finishing	2022	27
Analysis of Gate-Induced Drain Leakage Mechanisms in Silicon-Germanium Channel pFET Vishal A. Tiwari, D. Jaeger, A. Scholze, IEEE Transactions on Electron Devices Device ModelingElectrical EngineeringEngineeringPhysicsSubstrate Bias	2014	23
Hybrid low‐ <i>k</i> spacer scheme for advanced FinFET technology parasitic capacitance reduction Man Gu, X. Wang, W. Li, Electronics Letters Low-power ElectronicsDevice ModelingElectrical EngineeringMaterials ScienceEngineering	2020	18
New layout dependency in high-k/Metal Gate MOSFETs M. Hamaguchi, Deleep R. Nair, D. Jaeger, Electrical EngineeringPhysical Design (Electronics)EngineeringSemiconductor DeviceNew Layout Dependency	2011	13

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