R. Hasumi

Scaling of 32nm low power SRAM with high-K metal gate

Haining Yang, Robert Wong, R. Hasumi et al. · 2008 · 49 citations

Electrical Engineering, Engineering, Vlsi Design +14

Scalability of strained silicon CMOSFET and high drive current enhancement in the 40 nm gate length technology

T. Sanuki, A. Oishi, Y. Morimasa et al. · 2004 · 35 citations

Electrical Engineering, Strained Si Technology, Engineering +11

Comprehensive Study on Injection Velocity Enhancement in Dopant-Segregated Schottky MOSFETs

A. Kinoshita, Takenari Kinoshita, Yoshifumi Nishi et al. · 2006 · 21 citations

Device Modeling, Electrical Engineering, Semiconductor Device +9

Ultra Low Voltage Operations in Bulk CMOS Logic Circuits with Dopant Segregated Schottky Source/Drain Transistors

Takenari Kinoshita, R. Hasumi, M. Hamaguchi et al. · 2006 · 18 citations

Low-power Electronics, Electrical Engineering, Engineering +12

A high performance 100 nm generation SOC technology (CMOS IV) for high density embedded memory and mixed signal LSIs

Kazuo Miyashita, Takashi Nakayama, A. Oishi et al. · 2002 · 17 citations

Low-power Electronics, System On Chip, Electrical Engineering +13