Ultra Low Voltage Operations in Bulk CMOS Logic Circuits with Dopant Segregated Schottky Source/Drain Transistors

Abstract

Ultra low power circuit operation is demonstrated with dopant segregated Schottky (DSS) source/drain transistors for the first time. DSS greatly improves propagation delay in multiple fan-in NAND gates at constant standby current. The delay is enhanced to 21% at 0.8V for 3-input NAND gates. Energy delay product (EDP) is improved by more than 50% with DSS at 0.8V