S. Mittl

A high performance 90nm SOI technology with 0.992 μm/sup 2/ 6T-SRAM cell

Mukesh Khare, S.H. Ku, R. A. Donaton et al. · 2003 · 43 citations

Engineering, Computer Engineering, Electrical Engineering +17

Accelerated gate-oxide breakdown in mixed-voltage I/O circuits

T. Furukawa, Drew Turner, S. Mittl et al. · 2002 · 43 citations

Engineering, Electrical Engineering, Microelectronics +15

The combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in MOSFET's

T.G. Ference, Jay Burnham, William F. Clark et al. · IEEE Transactions on Electron Devices · 1999 · 42 citations

Engineering, Electrical Engineering, Materials Science +17

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm 2 SRAM and ultra low-k back end with eleven levels of copper

B. Greene, Qingqing Liang, K. Amarnath et al. · Symposium on VLSI Technology · 2006 · 40 citations

Engineering, Computer Engineering, Electrical Engineering +15

Process stability of deuterium-annealed MOSFET's

William F. Clark, T.G. Ference, Terence B. Hook et al. · IEEE Electron Device Letters · 1999 · 34 citations

Engineering, Electrical Engineering, Materials Science +17