M. Hargrove

Strained Si NMOSFETs for high performance CMOS technology

K. Rim, Steven J. Koester, M. Hargrove et al. · 2002 · 152 citations

Engineering, Electrical Engineering, Materials Science +15

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

P. Agnello, T. Ivers, C. Warm et al. · 2006 · 115 citations

Engineering, Computer Engineering, Electrical Engineering +17

Modeling line edge roughness effects in sub 100 nanometer gate length devices

P. Oldiges, Qimghuamg Lin, Karen Petrillo et al. · 2002 · 112 citations

Engineering, Electrical Engineering, Materials Science +17

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Siddarth Krishnan, U. Kwon, N. Moumen et al. · 2011 · 81 citations

Engineering, Computer Engineering, Electrical Engineering +17

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

M. Chudzik, B. Doris, R. Mo et al. · 2007 · 77 citations

Engineering, Computer Engineering, Electrical Engineering +17