M. Hargrove

Strained Si NMOSFETs for high performance CMOS technology

K. Rim, Steven J. Koester, M. Hargrove et al. · 2002 · 151 citations

Materials Engineering, Electrical Engineering, Semiconductor Device +11

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

P. Agnello, T. Ivers, C. Warm et al. · 2006 · 115 citations

Engineering, Vlsi Design, Enhanced Strain +21

Modeling line edge roughness effects in sub 100 nanometer gate length devices

P. Oldiges, Qimghuamg Lin, Karen Petrillo et al. · 2002 · 112 citations

Device Modeling, Electrical Engineering, Semiconductor Device +13

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Siddarth Krishnan, U. Kwon, N. Moumen et al. · 2011 · 81 citations

Sige Channels, Low Power Applications, Engineering +16

RF potential of a 0.18-μm CMOS logic device technology

Joachim N. Burghartz, M. Hargrove, C.S. Webster et al. · IEEE Transactions on Electron Devices · 2000 · 76 citations

Low-power Electronics, Electrical Engineering, Engineering +11